Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for manufacturing fin field effect transistors.
The need to remain cost and performance competitive in the production of semiconductor devices has driven the increase in device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies such as the in the design and fabrication of field effect transistors (FETs). FETs comprise the dominant components of CMOS. Scaling FETs to attain higher device density in CMOS results in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a fin Field Effect Transistor. In finFETs, the body of the transistor is formed from a vertical structure, generally referred to as a xe2x80x9cfinxe2x80x9d for its resemblance to the dorsal fin on a fish. The gate of the finFET is then formed on one or more sides of the fin. FinFETs have several advantages, including better current control without requiring increased device size. FinFETs thus facilitate scaling of CMOS dimensions while maintaining an acceptable performance.
Unfortunately, several difficulties arise in the design and fabrication of fin transistors. First, in fin transistors there is a general need to electrically isolate each finFET device. Specifically, finFET devices need to be isolated from each other, and the source and drain of individual devices need to be isolated to ensure source to drain decoupling. For this reason, finFETs have been typically manufactured from silicon-on-insulator (SOI) wafers to provide isolation between the fins of different devices. Specifically, the fins of the transistors are formed from the silicon layer above the buried isolation layer, and each fin is thus isolated from other fins by virtue of the buried isolation layer beneath the fins. Likewise the source and drains of individual finFETs are decoupled from each other by the buried isolation layer.
While the use of SOI wafers provides needed isolation for finFETs, it is not without significant drawbacks. The most compelling drawback of forming finFETs from SOI wafers is the added costs for SOI wafers compared to bulk silicon wafers. For example, SOI wafers can commonly cost two to three times the cost of bulk silicon wafers. This increased cost of SOI wafers, while acceptable for some applications, is prohibitive in others. Additionally, the use of SOI wafers is not compatible with all fabrication processes, such as commonly used SiGe processes.
The method of isolating devices on bulk wafers is described by Hisamoto et al, xe2x80x9cA fully Depleted Leanxe2x80x94channel Transistor (DELTA) xc3xa2∈xe2x80x9d A novel vertical ultra thin SOI MOSFET xc3xa2∈xe2x80x9dxe2x80x9d International Electron Devices Meeting 1989, Paper 34.5.1, pp 833-6. This method requires that a nitride spacer be built on the fin so that the fin is protected during the oxidation of the underlying substrate to form the region of isolation. Thus, the substrate is selectively oxidized with respect to the fin. The limitations of this process are the high temperature of the oxidation, 1100xc2x0 C., and the inability to tailor the fin thickness while generating the isolation layer. As devices continue to scale their ability to withstand high temperature conditions decreases; as such, the process proposed in Hisamoto et al is incompatible with the nanoscale technologies in which FinFETs will find their use. Moreover, the inability to tailor fin thickness means that a critical dimension of these devices is solely determined by lithography. As will be discussed in more detail below, a feature of the method of the invention is that it provides the ability to tailor the fin via oxidation, enabling the optimization of fin thickness beyond lithographic capabilities.
Additionally, Hisamoto""s process does not provide a method to control fin height. Bulk wafers lack a layer upon which the etch of the fin can terminate, such as is provided by the buried oxide layer in SOI wafers. Without this etch stop layer, variability in the etch depth translates to variability in the fin height. Since the amount of current conducted by the device is proportional to the height of the fin, it is important to minimize variability in the fin height.
Thus, there is a need for improved fabrication methods and structures to facilitate the formation of finFET devices from bulk silicon while minimizing device variations and providing sufficient device isolation.
The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved device uniformity.
In a first aspect, the invention is a method for forming a finFET in semiconductor substrate, the method comprising the steps of forming a fin from the semiconductor substrate; and exposing the substrate to a process that further defines the width of the fin while simultaneously isolating the fin.
In a second aspect, the invention is a method for forming a finFET in semiconductor substrate, the method comprising the steps of forming a fin from the semiconductor substrate, the fin including a fin sidewall, the formation of the fin exposing areas of the semiconductor substrate adjacent the fin; damaging at least a portion of the semiconductor substrate areas adjacent the fin; and oxidizing the semiconductor substrate such that oxide is formed in the damaged portion of the semiconductor substrate to a greater thickness than is formed on the fin sidewall.